Toshiba Looking At Ways To Squeeze Five Bits Per Cell From Standard TLC Flash

Toshiba Looking At Ways To Squeeze Five Bits Per Cell From Standard TLC Flash
Credit: Toshiba

Toshiba has announced that it’s diving into a Penta-level cell capability to expand the density of current NAND flash standard. This was revealed during the recent Flash Memory Summit, as shared by the report from Tom’s Hardware.

For those unfamiliar with how NAND flash memory works, they have several types, each with its distinct functionality and purpose.

SSD manufacturers have long been trying to upend HHDs in terms of storage density. The data transfer of performance of SSDs compared to just a few years ago is like day and night. So the next step is for manufacturers to try to add more storage capacity to the SSD.

Flash memories work well due to the data transfer capability, quicker application load times, and faster boot rates. Another advantage is that they have fewer moving parts. That means they consume less energy and less vulnerable to damage.

The standard flash memory packs three-bits per cell (TLC). This has been the standard for a long time because it’s cheaper than the SLC and MLC. SLC and MLC, of course, refer to the single-level cell and multi-level cell, respectively. However, you have now the QLC or the quad-level cell.

For a long time, SSDs have earned a reputation for easily breaking down. In recent years, however, manufacturers have optimized these NAND drives that endurance can be overlooked. While they are still less durable compared to HHDs, consumers are now getting their money’s worth.

But why is nobody doing what Toshiba is attempting to come up with a Penta-level cell (PLC)?

Well, it all comes down to the challenge, said PCGamesN.

For instance, each cell has to store 32 distinct voltage levels, which then needed to be read by SSD controllers. Not only will the controller read them at lightning speeds, but it must do so accurately. The challenge is the total quantity of the voltage levels at such a small scale.

Toshiba needs to come up with new processes to serve as a bridge for the TLC and QLC.

And there’s another thing that needed to be addressed. The higher the bits per cell, the slower the flash seems to be going. There’s also a question of endurance since the QLC doesn’t really last that long.

If Toshiba can’t make some remedial measures, the PLC is expected to be even slower and more brittle. Accordingly, Zoned Namespaces, an NVMe protocol, might help arrest the problem, especially in the areas of latency and throughputs.